1. Field of the Invention
The present invention relates to a method for producing a semiconductor substrate, and more particularly a method for producing a semiconductor substrate adapted for the formation of an electronic device or an integrated circuit in a single-crystal semiconductor layer on a dielectric separation layer or an insulator, or in a single-crystal compound semiconductor on an Si substrate.
2. Related Background Art
The formation of a single-crystal Si semiconductor layer on an insulator is widely known as semiconductor-on-insulator (SOI) technology, and various research has been made because the device utilizing the SOI technology has various advantages that cannot be attained with the use of a bulk Si substrate in the preparation of ordinary Si integrated circuits. More specifically, the use of the SOI technology provides the following advantages:
1. dielectric separation can be easily conducted to attain a higher degree of integration;
2. radiation resistance is excellent;
3. stray capacitance can be reduced to attain a higher speed;
4. a well forming step can be omitted;
5. latch-up can be prevented; and
6. a fully depleted field effect transistor can be made by thin film formation.
These features are detailed, for example, in Special Issue: xe2x80x9cSingle-crystal silicon on non-single-crystal insulatorsxe2x80x9d, edited by G. W. Cullen, Journal of Crystal Growth, Vol. 63, No. 3, pp.429-590 (1983).
Also in recent years, many reports have been published on the SOI substrate for realizing higher speed and lower power consumption in the MOSFET (IEEE SOI conference 1994). Also use of the SOI substrate allows for the shortening of device process steps, since the presence of an insulator layer under the device simplifies the device isolation process in comparison with the case of device formation on a bulk Si wafer. Thus, in comparison with the MOSFET or IC formed on bulk Si, a total reduction of the wafer cost, and the process cost, together with a higher performance, is expected.
In particular, the fully depleted MOSFET is expected to achieve higher speed and lower power consumption by improvement of a driving power. The threshold voltage (V+h) of the MOSFET is generally determined by the impurity concentration of the channel portion, and in case of the fully depleted MOSFET utilizing the SOI structure, the thickness of the depletion layer is also affected by the film thickness of SOI. Consequently, in order to produce large-area integrated circuits with high production yield, there has strongly been desired uniformity of SOI film thickness.
Also the devices formed on the compound semiconductor have excellent features, such as high speed or light emission, which are not achievable with the silicon substrate. Presently such devices are mostly formed by epitaxial growth on a compound semiconductor substrate such as GaAs or the like. However, such a compound semiconductor substrate has drawbacks related to expense, low mechanical strength, difficulty of preparation of a large area wafer and the like.
In view of such a situation, there has been made an attempt to heteroepitaxially grow a compound semiconductor on the silicon wafer which is inexpensive, mechanically strong and can be easily prepared with a large area.
Investigations on the formation of the SOI substrate have been active since the 1970""s. In the initial period, there have been investigated a method of heteroepitaxially growing a single-crystal silicon on an insulating sapphire substrate (SOS: silicon on sapphire) and a method of forming the SOI structure by dielectric separation utilizing oxidation of porous Si (FIPOS: full isolation by porous oxidized silicon).
The FIPOS method consists of forming islands of n-type Si layer on the surface of a p-type single-crystal Si substrate by proton implantation (Imai et al., J. Crystal Growth, Vol. 63, 547 (1983)) or by epitaxial growth and patterning, then making only the p-type Si substrate porous by anodizing in HF solution so as to surround the Si islands from the surface side and achieving dielectric isolation of the n-type Si islands by accelerated oxidation. Since in this method the isolated Si islands are determined prior to the device manufacturing step, the freedom of device designing may be limited.
An oxygen ion implantation method referred to as the SIMOX method was originally reported by K. Izumi. After oxygen ions are implanted with a concentration of 1017 to 1018/cm2 into an Si wafer, it is annealed at a high temperature of about 1320xc2x0 C. in an argon-oxygen atmosphere, whereby the implanted oxygen ions combine with Si atoms around a depth corresponding to the projected stroke (Rp) of the ion implantation to form a silicon oxide layer. In this operation, an Si layer present on the oxidized silicon layer and made amorphous by oxygen ion implantation recrystallizes to form a single-crystal silicon layer. The number of defects in the surface Si layer was as high as 105/cm2, but has been reduced to about 102/cm2 by maintaining the implanted amount of oxygen ions at about 4xc3x971017/cm2. However, since the implantation energy and the implantation amount are limited to a. narrow range in order to maintain desired film quality of the Si oxide layer and desired crystallinity of the surface Si layer, the thicknesses of the surface Si layer and the buried Si oxide (BOX: buried oxide) layer have been limited to specified values. Therefore, for obtaining the surface Si layer of a desired film thickness, it has been necessary to effect sacrifice oxidation or epitaxial growth. In such a case, there is a problem that the uniformity of the film thickness inevitably deteriorates, since the deterioration of the uniformity of the film thickness due to such a process is added to the original film thickness distribution.
It has also been reported that the BOX layer contains a region, called a xe2x80x9cpipexe2x80x9d, of defective Si oxide formation. One of the causes of such a defective formation is foreign matter such as dust at the implantation. In the portion of such a pipe, there is generated a leak between an active layer and a supporting substrate which deteriorates the device characteristics.
The ion implantation of the SIMOX method with a larger amount of implantation in comparison with that in the ordinary semiconductor process requires a long implantation time even when using an apparatus developed exclusively for this purpose. Since the ion implantation is conducted by rester scanning with an ion beam of a predetermined current or by expanding an ion beam, it is anticipated to require a longer time with an increase in the area of the wafer. Also the high-temperature heat treatment of a wafer having a large area is anticipated to become more difficult, because of the generation of problems such as slip due to the temperature distribution within the wafer. As the SIMOX method requires a heat treatment at 1300xc2x0 C. or higher which is not usually employed in the Si semiconductor process, there is concerned an increase in the problems to be solved such as apparatus development, metal contamination and slip.
In addition to the conventional SOI forming methods described above, there is recently contemplated a method of bonding a single-crystal Si substrate to another thermally oxidized single-crystal Si substrate by heat treatment or with an adhesive to obtain the SOI structure. In this method, an active layer for device formation has to be formed as a uniform thin film. Stated differently a single-crystal Si substrate of a thickness of several hundred micrometers has to be formed as a thin film on the order of a micrometer or less. This formation of the thin film is conducted by three methods as described below:
1. thin film formation by polishing;
2. thin film formation by local plasma etching; and
3. thin film formation by selective etching.
By the above method 1, it is difficult to provide a uniform thin film by polishing. In particular, fluctuation in thickness becomes as high as several tens of percent when forming a thin film of sub-micron thickness, and the formation of a uniform thin film becomes a large problem. The difficulty of forming a thin film becomes more severe with an increase in a wafer diameter.
In the above method 2, after forming a thin film of about 1 to 3 xcexcm by the grinding of method 1, thickness distribution is measured in many points over the entire surface and then plasma etching is conducted while scanning a plasma beam of a diameter of several mm, for example, of SF6 to correct the thickness distribution on the basis of the measured distribution, thereby forming a thin film of a desired thickness. It is reported that this method has achieved a film thickness distribution of about xc2x110 nm. However, if a particle is present on a substrate during the plasma etching, such a particle functions as an etching mask, so that a projection is formed on the substrate.
Also as the surface after the plasma etching is coarse, a touch polishing operation is required after the plasma etching, but the difficulty in the control of the final film thickness and the deterioration of the film thickness distribution by the polishing operation are noted since the polished amount is controlled by the polishing time. Besides, as the polishing material such as colloidal silica comes into direct contact with the surface of an active layer in the polishing operation, there are concerns regarding the formation of a crushed layer and the generation of a working strain due to the polishing operation. Furthermore, as the wafer area becomes larger, the plasma etching time increases proportionally with an increase in the wafer area, possibly leading to a significant decrease in a throughput.
The above method 3 consists of providing in advance a substrate to be formed into a thin film structure which can be selectively etched. For example, on a p-type substrate, a thin p+-type Si layer containing boron atoms at a concentration of 1019/cm3 or more and a thin p-type Si layer are stacked, for example, by epitaxial growth to obtain a first substrate. This substrate is adhered to a second substrate with interposition of an insulating layer such as an oxide film, and the first substrate is made thin by grinding and polishing from the rear surface. Subsequently the p-type layer is selectively etched to expose the p+-type layer, and the p+-type layer is then selectively etched to expose the p-type layer, thereby completing the SOI structure. This method is reported in detail by Maszara (W. P. Maszara, J. Electrochem. Soc., Vol. 138, 341 (1991)).
The selective etching method is considered effective for obtaining a uniform thin film, but has the following problems.
(1) A selective ratio is about 102 and is not sufficient.
(2) Touch polishing is necessary after the etching because the surface after the etching is coarse. As a result, however, the uniformity of film thickness tends to deteriorate with a decrease in film thickness. Also the polishing amount is controlled by the polishing time, but is difficult to control because of the fluctuation in the polishing rate. This is particularly a problem in the formation of an ultra thin SOI layer such as of 100 nm.
(3) The crystallinity of the SOI layer is insufficient because the ion implantation, epitaxial or heteroepitaxial growth is conducted on the high-concentration boron-doped Si layer. Also the property of the surface to be bonded is inferior to that of the ordinary Si wafer.
The above points are reported by C. Harendt et al., J. Elect. Mater., Vol. 20, 267 (1991), H. Baumgart et al., Proceeding of the 1st International Symposium on Semiconductor Wafer Bonding: Science, Technology and Applications, (The Electrochemical Society) Vol. 92-7, p.375, and C. E. Hunt et al., Proceeding of the 1st International Symposium on Semiconductor Wafer Bonding: Science, Technology and Applications (The Electrochemical Society) Vol. 92-7, p.165.
Also the selectivity of the selective etching greatly depends on a difference in a concentration of the impurity such as boron and the profile steepness of the impurity in the direction of depth. Therefore, if there is conducted a high-temperature bonding annealing for increasing a bonding strength or a high-temperature epitaxial growth for improving crystallinity, the distribution of the impurity concentration is spread in the direction of depth, thereby deteriorating the etching selectivity. That is, the improvement in the etching selectivity has not been compatible with the improvement in the crystallinity and in the bonding strength.
Recently Yonehara et al. reported a bonding SOI method which is free from the above problems and is excellent in film thickness uniformity and in crystallinity and which enables a batch process (T. Yonehara et al., Appl. Phys. Letter, Vol. 64, 2108 (1994)). This method employs a porous layer 32 on a first Si substrate 31 as a material for selective etching. After a non-porous single-crystal Si layer 33 is epitaxially grown on a porous layer, it is bonded to a second substrate 34 via an Si oxide (insulator) layer 35 (FIG. 5A). The first substrate is made thin, for example, by grinding from the rear surface to expose the porous Si layer over the entire area of the substrate (FIG. 5B). The exposed porous Si is removed by etching with a selective etching solution such as KOH or HF+H2O2 (FIG. 5C). In this operation, the selective ratio of the etching of porous Si to bulk Si (non-porous single-crystal Si) can be made as high as 100,000 times so that an SOI substrate can be formed by leaving, on the second substrate, the non-porous single-crystal Si layer grown in advance on the porous layer, without any substantial change in the film thickness. Therefore, the film thickness uniformity of SOI can be substantially determined by the epitaxial growth operation. As the epitaxial growth can be conducted in a CVD apparatus employed in the ordinary semiconductor process, there has been achieved a uniformity, for example, of 100xc2x12% according to the report of Sato et al. (SSDM 95). Also it has been reported that the crystallinity of the epitaxial Si layer is a satisfactory value of 3.5xc3x97102/cm2.
Porous Si was found by Uhlir et al. in 1956 in the course of an investigation of electropolishing of a semiconductor (A. Uhlir, Bell Syst. Tech. J., Vol. 35, 333 (1956)). The porous Si can be formed by anodization of an Si substrate in HF solution and has a sponge-like shape having minute pores which is formed from bulk Si by electrolytic etching. The pores have a diameter of about several nanometers and are formed with a density, for example, of 1011/cm2, though these are variable depending on the conditions of anodization and the specific resistivity of Si.
Unagami et al. have investigated the dissolution reaction of Si upon anodization and reported that the anodization reaction of Si in HF solution requires positive holes. The reaction is as follows (T. Unagami, J. Electrochem. Soc., Vol. 127, 476 (1980)):
Si+2HF+(2xe2x88x92N)e+xe2x86x92SiF2+2H++nexe2x88x92
SiF2+2HFxe2x86x92SiF4+H2 
SiF4+2HFxe2x88x92H2SiF6 or
Si+4HF+(4xe2x88x92xcex)e+xe2x86x92SiF4+4H++xcexexe2x88x92
SiF4+2HFxe2x86x92H2SiF6 
wherein e+ and exe2x88x92 represent a positive hole and an electron, respectively. Also n and xcex are the number of positive holes required for dissolving one Si atom, and it has been reported that porous Si is formed under a condition of n greater than 2 or xcex greater than 4.
According to this report, p-type Si containing positive holes can be made porous but n-type Si is not made porous. This selectivity of the porous structure formation has been proved by Nagano et al. and Imai (Nagano, Nakajima, Yasuno, Ohnaka and Kajiwara, Technical Research Report of Electronic Communications Society, Vol. 79, SSD79-9549 (1979); and K. Imai, Solid-State Electronics, Vol. 24, 159 (1981)).
In the conventional method, the selectivity of etching depends on a difference in an impurity concentration and a profile thereof in the depth direction, so that the temperature of heat treatment (in bonding, epitaxial growth, oxidation, etc.) which spreads the distribution of the concentration is limited to about 800xc2x0 C. or lower. On the other hand, in this method, since the etching rate is determined by a difference between the porous structure and the bulk structure, the heat treatment involves little limitation in the heat treatment temperature and has been reported achievable at about 1180xc2x0 C. For example, the heat treatment after bonding is known to increase the bonding strength of the bonded wafers and to decrease the number and the size of the voids generated in the bonding interface. Also in the etching based on such a structural difference, particles eventually deposited on the porous Si do not influence the uniformity of film thickness.
Also in case of a light-transmissive substrate generally having an irregular crystalline structure such as glass, a thin Si film deposited thereon usually becomes amorphous or polycrystalline at best, reflecting the crystalline irregularity of the substrate, so that a high-performance device cannot be prepared on such a substrate. This is based on a fact that the substrate is amorphous, and therefore a satisfactory single-crystal layer cannot be obtained by merely depositing an Si layer thereon.
On the other hand, the semiconductor substrate employing the bonding method always requires two wafers, one of which is mostly removed by polishing or etching, thus leading to increased cost and eventually resulting in significant waste of limited resources.
For this reason, in order to exploit the features of SOI employing the bonding process, there has been desired a method capable of reproducibility providing an SOI substrate of satisfactory quality and at the same time realizing the saving of resources and cost reduction, for example, by reuse of the wafers.
Recently Sakaguchi et al. has reported a method of reusing a first substrate which is consumed in a bonding step (Japanese Patent Application Laid-Open No. 07-302889).
In the above method of conducting bonding and etch-back by using porous Si, they adopted the following method instead of the step of exposing porous Si by polishing or etching the first substrate from the rear surface thereof.
After the surface region of a first Si substrate 41 is made porous to form a porous layer 42, a single-crystal Si layer 431s formed thereon, and this single-crystal Si layer 43 is adhered via an insulating layer 45 to the main face of a second Si substrate 44 which is separate from the first substrate 41 (FIG. 6A). Then the bonded wafers are divided by the porous layer (FIG. 6B), and the porous Si layer remaining on the surface of the second Si substrate is selectively removed by etching to obtain an SOI substrate (FIG. 6C). The division of the bonded wafers is achieved by destruction of the porous Si layer by:
applying a sufficient and uniform tensile force or pressure to the whole of the wafers in a direction perpendicular to the inside face of the bonded wafers;
applying a vibration energy such as an ultrasonic wave;
exposing the porous layer at the edge of the wafers, etching the exposed portion of the porous Si layer by a certain amount and inserting a razor blade or the like into such an etched portion;
exposing the porous layer at the edge of the wafers, impregnating the porous Si layer with liquid such as water, and heating or cooling the entirety of the bonded wafers to cause expansion of the liquid; or
applying a force to the first (or second) wafer in a direction parallel to the second (or first) substrate.
These methods are based on a fact that though the mechanical strength of porous Si is dependent on the level of porosity, it is believed that the strength is sufficiently lower than that of bulk Si. For example, if the porosity is 50%, the mechanical strength of a porous layer is considered to be about half that of bulk Si. Thus, if a compressing force, a tensile force or a shearing force is applied to the bonded wafers, the porous Si layer is broken first. The porous layer can be broken with a weaker force by an increase in the level of porosity.
The porosity is defined as the percentage of pore volume with respect to the apparent volume of a porous layer, that is, the sum of the volume of a material constituting the porous layer and the pore volume.
However, in the method disclosed in the Japanese Patent Application Laid-Open No. 07-302889, the position of separation within the thickness of the porous layer in a thickness direction cannot be defined, so that the wafer yield deteriorates in some cases because such a position of separation varies in each wafer. Besides, the thickness of the porous Si layer remaining after separation of the wafers has significant fluctuation. Therefore, even using highly selective etching, the wafer yield was deteriorated in some cases in order to satisfy the requirement for the highly uniform film thickness for SOI.
Also the Japanese Patent Application Laid-Open No. 8-213645 describes a method of separation by the porous layer, but does not describe the layer structure of the porous layer. Separately, Tanakaya et al. of Sony reported, in Preprints for 1996 Fall Congress of Applied Physics Society, p.673, the preparation of porous Si by a change in the current in the course of processing.
The Japanese Patent Application Laid-Open No. 8-213645 describes that the separation takes place at any position of the separation layer; that is, that the separating position cannot be defined. In such case, the thickness of the remaining porous Si layer fluctuates over the wafer, and, when the porous Si is removed by etching, an active layer (device forming layer) is more or less etched also to result in a fluctuating thickness in the plane of the wafer as long as the etching rate for the active layer consisting of a non-porous single crystal is not zero. Also even if the remaining porous Si is left, the surface step coverage resulting from the separating position is left on the wafer. Also the method described in the above-mentioned Preprints for 1996 Fall Congress of Applied Physics Society, p.673 describes that the separation takes place by the center portion of the porous Si, so that the porous Si layers remaining on both wafers have to be removed.
For preparing the bonding SOI substrate of satisfactory quality, the etching step of the porous layer has been considered to be essential. The etching step requires conveyance of the substrate into and from the etching apparatus, management of the etching apparatus and etchant, rinsing of the substrate after etching, etc. Therefore the preparation time of the SOI substrate can be significantly reduced if the etching step can be omitted.
An object of the present invention is to provide a method of producing a substrate, which is capable of omitting a selective etching step of the porous layer.
Another object of the present invention is to provide a method for inexpensively preparing a semiconductor substrate of satisfactory quality, represented by the SOI substrate.
The present invention provides a method for producing a substrate, comprising:
preparing a first substrate member and a first layer and a second layer provided on and adjacent to the first layer;
bonding the first substrate member to a second substrate member; and
separating the first substrate member and the second substrate member to transfer the second layer onto the second substrate member, wherein the separation of the first substrate member and the second substrate member is conducted at the interface between the first layer and the second layer.